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Insight SiP serves the market with turn-key design services and creative packaging solutions to customers who need highly integrated systems to meet wireless and portable devices space requirements. IT’S ALL IN THE PACKAGE! IN SHORTER TIME!

Phone: +33 (0) 493 008 880

GreenSide, Bat.7, Entree2,
400 Avenue Roumanille, BP 309
F-06906 Sophia–Antipolis FRANCE

Design methodology

Insight SiP’s methodology is based on a user extendable library of physical objects for which the electrical models are created automatically for a given stack-up and/or technology. Thus any design that is initially made for a particular supplier can easily be re-tuned for an alternative source. The method uses a combination of circuit and EM simulations to create a design progressively from basic schematic representation to a complete layout.
2.5D or 3D EM simulations are used for the passive integrated functions (laminate, IPD, LTCC, PCB) and harmonic balance or device modeling for the active circuits. The functionality that is contained within buried functions inside the substrate is created using an iterative process.

- First step:
It is to create for a given technology a range of parameterized mechanical objects.
These objects allow simple RF functions, such as capacitors, inductors and resonators, to be created. - Second step:
It is to couple the technology file for the target process to the mechanical objects.
A series of batch based electromagnetic simulations of the mechanical objects within the desired technology file framework creates data for a look-up table based model for each component (L, C or more complex resonator element).
It allows for the creation of a set of project and technology related schematic objects that can be optimized to produce the required RF functionality.
Simulations using these models can be carried out in both the frequency domain and the time domain. At this level of the design, circuit optimization is carried out to determine the parameters of the schematic/mechanical object. This process is quite similar to that carried out in semiconductor design using library based objects that have electrical performance and create layout. - Third step:
The third step of the process is to create complete sections of physical layout with the mechanical objects using the circuit optimization parameters.
A closed loop iterative process is used to obtain final layout that has the same electrical performance as the sum of the modelled portions. At this stage coupling effects between blocks are compensated for. This has the advantage of allowing the mechanical objects to be placed close together without any risk of causing unseen effects. This makes the designs created by this method more compact than those using a “P Cell” approach with large keep-out zones to avoid coupling.

Download the Design Process presentation     Insight SiP - Design Process.pdf
 

Example - Design methodology applied to a GSM Low Pass Filter

- Build a parameterized component library (cf.  1st step)
- Simulate the inductor and capacitor components using Momentum 2.5D simulator for various geometrical parameters (Width, Diameter, ...)
- Optional: Extract equivalent model parameters for each geometry
- Build a parameterized simulation model based on individual geometries

inductor image14

-  Choose a filter topology (Chebychev for ex.) with ideal lumped components
-  Optimize L, C component values to match specifications -  Generate the target schematic for the filter (cf. 2nd step)
-  with the parameterized library component
-  Tune/optimize the object dimensions to match ideal s-parameter response

schema2

-  Preliminary layout/ Fast iterative process/ Final layout (cf.  3rd step)
-  Generate a preliminary layout and simulate
-  Optimize the component dimensions in order to match the target response
-  Final momentum simulations
-  Gerber file generations

layout

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Insight SiP
GreenSide, Bat.7, Entree2,
400 Avenue Roumanille, BP 309
F-06906 Sophia–Antipolis FRANCE

Phone: +33 (0) 493 008 880

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